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x86 Assembler Simulator for Education
Heštera, Andrej ; Semerád, Lukáš (referee) ; Orság, Filip (advisor)
Point of this thesis is gain knowledge base of x86 Instruction Set Architecture and x86 assembly language through analysis. Based on this knowledge, design and implement simulation environment in object oriented programming language Java SE8. This environment will give user option to create code based on conventions and syntax of Netwide Assembler and simulate created code on virtual representation - simulation model, which will imitate behavior of processor implementing instruction set architecture x86. The result of using this environment should be new knowledge for user about basic function of machine code execution and how this execution alters state of processor, without the need to specially compile created code for use in Debugger and having physical system implementing architecture x86.
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Windows PE Transformation into Control Flow Graph
Jirák, Ota ; Burget, Radek (referee) ; Kolář, Dušan (advisor)
This thesis is interested in format of executable files EXE. It is focused on parts relevant for reverse engineering. It is interested in assembler, binary representation of instruction and disassembling. Follow I introduce converting from executables to control flow graph, basic structures (branches, cycles) detection.
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Native Code Web Browser Extensions
Vítek, Vojtěch ; Očenášek, Pavel (referee) ; Burget, Radek (advisor)
Nowadays, web applications and browsers are undergoing rapid development - we can say that the progress of Internet technologies is unstoppable phenomenon of the last decade. The need for the best-possible CPU performance in web applications to achieve a smooth user experience is enormous - besides the continuous improvements of existing technologies, we can see several new technologies arising every year. This thesis deals with development of native code web browser extensions whose primary purpose is to use maximum CPU performance as well as efforts to improve the user experience when viewing web pages.
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A CPU Emulator for Assembler Course
Charvát, Lukáš ; Nagy, Jan (referee) ; Smrčka, Aleš (advisor)
The bachlors's thesis discusses the design of a CPU architecture emulator aimed to assembly languages course. While most of nowadays emulators are architecture specific, this document describes an approach to create an emulator allowing users to easily set up their own architecture, to perform operations upon it, and to display its current state.
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Translation to Various Assembly Languages
Hranáč, Jan ; Goldefus, Filip (referee) ; Meduna, Alexandr (advisor)
The goal of this project is to create a compiler capable of compilation of the input language into various assemblers (by the choice of the user). This will be achieved by expandibility of the compilator by modules implementing the building of the source files of the concrete types of assembler. The compilator will serve as a generator of parts of assembler source codes to make the work of assembler programmer easier. The input language is derived from Pascal but is closer to assembler then canonical Pascal.
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Visualising CPU Activity
Ďurčo, Marián ; Češka, Milan (referee) ; Vojnar, Tomáš (advisor)
This thesis is intended to be a complement for learning about the RISC pipeline. Product of this thesis is a web application. After reviewing various tools and libraries suitable for this work, we have chosen two main libraries React and Redux. The created solution allows the instruction flow to be displayed in the RISC pipeline as well as states of the registers and the memory. It makes easy to perform transitions between the various parts of the visualization. This visualization allows a basic understanding of the RISC pipeline principles and also individual assembly instructions.
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Emulator of Simple Processor
Kuzník, Petr ; Přikryl, Zdeněk (referee) ; Křoustek, Jakub (advisor)
Emulator will be designed as generic emulator. It should be capable of emulating versatile architectures. Each architecture will be stored in separate module implemented as dynamically linked dll libraries. Main goal is for the emulator to be generic and design its structure in a way, so that it would be possible to easily add new architecture modules and design these modules with already implemented abstractions. Primarily implemented architecture will be Commodore 64. It is a personal computer used mainly in USA during 1980s.
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A frequency inverter based on Texas Instruments DSP
Vašíček, Adam ; Macho, Tomáš (referee) ; Valach, Soběslav (advisor)
This bachelor thesis is focused on control algorithms optimization, especially using the Texas Instruments c2000 digital signal controllers family. The first part roughly describes an AC induction motor controlling and regulation techniques. Later on the control software optimization basics are covered. Particular attention is payed for trigonometric functions which are mandatory for such software. Next part shows practical use of the previously described optimization techniques using an example of the scalar frequency inverter control even going down to the assembly instructions level. At the end the results themselves as well as facing the invested price of optimization are discussed.
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A CPU Emulator for Course of Assembly Languages
Charvát, Lukáš ; Samek, Jan (referee) ; Smrčka, Aleš (advisor)
The master thesis discusses the design of an emulator of a CPU architecture instruction set aimed at assembly languages course. While most of nowadays emulators are architecture specific, the emulator proposed in master thesis aims at education and better understanding of assembly languages. The emulator is not limited to a single CPU, but it easily allows defining a purpose-specific architecture and instruction set in order to perform operations upon it and to display its current state.
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